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fDesc[0] = "Designer is Actel&#039;s powerful physical implementation software tool suite for all Actel FPGAs. After completing design entry and functional verification using Libero Integrated Design Environment (IDE) tools, import the resulting netlist into Designer to set timing constraints, run place-and-route, and perform timing analysis, power analysis, and program file generation. <br /> Designer software is included in Libero IDE and is installed automatically as part of a standard Libero IDE installation&dagger;. To use only Designer, download Libero IDE v9.1. In the installation wizard, select the &quot;Install Libero Standalone&quot; option.";

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