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fDesc[0] = "ADIsimCLK is the design tool developed specifically for Analog Devices&#039; range of ultra-low jitter clock distribution and clock generation products.<br /> <br /> Main features:<br /> - jitter performance - broadband and SONET specifications.<br /> - phase noise performance.<br /> - phase noise impact - ACI/ACR, EVM, phase jitter etc.<br /> - jitter impact on ADC performance - SNR, ENOB. - accurate timing analysis (logic analyzer display).";

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