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fDesc[0] = "A tool for creating fast, predictable designs with ATA6625 AT40K, AT40KAL, and AT6000 series FPGAs using HDL Planner for VHDL and Verilog Entry. This tool can be used with other popular synthesis tool environments. The IDS is available as a standalone tool, or integrated into system designer software as a complete package for FPSLIC/FPGA.";

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