var fDesc=new Array();
fDesc[0] = "PAC-Designer is a complete design and verification solution supporting platform management, power management and programmable clock device families. <br /> PAC-Designer has fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices.<br /> <br /> Main Features :<br /> - Fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices<br /> - High level logic design mechanism<br /> - Easy-to-use GUI<br /> - For Platform Manager it works in conjuction with ispLEVER to form a complete CPLD/FPGA design environment<br /> - Works with other Lattice software support tools such as IP Express<br /> - Hierarchical design entry <br /> - High level design entry for flexible power management <br /> - Design utilities";

function tShowHide(id, show)
{
	var s = document.getElementById("desc");

	if ((s.innerHTML.length<=212 || show==1) && show!=2)
	{
		s.innerHTML = fDesc[id];
		if (document.getElementById('m1'))
			document.getElementById('m1').style.display='none';
		if (document.getElementById('m2'))
			document.getElementById('m2').style.display='none';
		if (document.getElementById('more_txt'))
			document.getElementById('more_txt').style.display='inline';
	}
	else
	{
		s.innerHTML = '';
	}
}