Aldec active-hdl 9.1 in Title/Summary
Aldec ALINT
The tool features highly customizable and intuitive framework that seamlessly integrates into existing environments and helps to automate any existing design guidelines. ALINT design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage.
- Publisher: Aldec, Inc.
- Last updated: May 23rd, 2012
Aldec ALINT SR1
Features: -Fast design analysis of complex ASIC/FPGA/SOC designs -Phase-Based Linting (PBL) Methodology -IEEE VHDL, Verilog and mixed-language designs -STARC VHDL or Verilog rule plug-ins -DO-254/ED-80 VHDL or Verilog rule plug-ins -RMM rule plug-in -Custom rule creation -Integrated result analysis and debugging environment
- Publisher: Aldec, Inc.
- Last updated: November 9th, 2011
Aldec Active-HDL Student Edition
Active-HDL Student Edition is a mixed language design entry and simulation tool offered at no cost by Aldec to the students to use during their course work. Key Features of Active-HDL Student Edition: - Mixed language simulator - Multi-FPGA & EDA Tool Design Flow Manager - Graphical Design entry & editing - Code2Graphics and Graphics2Code - Pre-compiled FPGA vendor libraries
- Publisher: Aldec, Inc.
- Home page: www.aldec.com
- Last updated: July 19th, 2012
Aldec active-hdl 9.1 in Description
ispLEVER
ispLEVER is the previous generation design environment for Lattice FPGA products. It includes a comprehensive set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis, and more. ispLEVER is provided for Windows or Linux platforms. ispLEVER is supported for existing customers.
- Publisher: Lattice Semiconductor Corporation
- Last updated: February 16th, 2012
Additional Aldec active-hdl 9.1 selection
Active-HDL
Active-HDL is a Windows based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
- Publisher: Aldec
- Home page: www.aldec.com
- Last updated: May 19th, 2015
