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State machine diagram for timetable in Title/Summary

Timetable

Timetable

TimeTable is a tool for anyone who needs a visual timetable. It provides an easy way of scheduling the events for each of the maximum 20 timebars. With use of dragging, cut, copy & paste and multiple selections you can easily schedule your events. By working on the timetable in a visual way you can easily see overlapping events.

TimeTable Manager

TimeTable Manager

The timetable manager helps you organize your schedule in order to create a balance between your course at the university and your free time. The software has a very user friendly interface and is very easy to use. Organize your time now with the timetable Manager

  • Publisher: Jack Valmadre
Tswela Timetable

Tswela Timetable

The Tswela Timetable System allows you to generate and setup a timetable that matches the specific needs of your school in no time.Colour-coding, following the easy menu-based breadcrumbs and circling of selected menu items, eliminate any confusion in the step-by-step simple process.

  • Publisher: Tswela Services

State machine diagram for timetable in Description

StateBuilderDotNet

StateBuilderDotNet

StateBuilderDotNet is a state machine code generator for C# and VB.NET, it transforms a state machine description into an extended version of the state pattern. The state machine description, also known as state machine model, is written in a simple XML format, that is both human readable and writable.

  • Publisher: StateForge
  • Last updated: November 7th, 2011
Synplicity Synplify & Synplify Pro

Synplicity Synplify & Synplify Pro

Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic.

  • Publisher: Synplicity Inc
  • Last updated: September 14th, 2012
Logic Builder SDK

Logic Builder SDK

Features: -Event-driven state machine -Supported mode-types: Exclusive, Concurrent, No default child. -Multiple trees. -Events with arguments. -Mode-trees info stored as binary or "C" file. -Data-driven multilingual code generator. -Excel toolbar (GUI). -Find & Replace tool with auto-backup. -Trace in Excel. -Advanced Win32 Graphics Library (primitives for Win32 simulations).

  • Publisher: Timur Software
  • Home page: sites.google.com
  • Last updated: December 20th, 2009
Latin Thaana Converter

Latin Thaana Converter

Latin Thaana Converter is a small, simple software for Microsoft Windows that performs transliteration on latinized (romanized) Thaana to convert it back into the Thaana script. Latin Thaana Converter utilizes a finite state machine and its transliteration mappings are based on a more extensive scheme extracted from an analysis of a body of Latin Thaana-to-Thaana sample data.

  • Publisher: Jawish Hameed
  • Home page: www.jawish.org
  • Last updated: October 23rd, 2009
Ventuz

Ventuz

Ventuz is a professional tool for high-end 3D multimedia presentations. It is the perfect solution for presentations given in a business or event surrounding, where every aspect, from location over decoration to catering, has been arranged by specialists.

  • Publisher: Ventuz Technology
  • Last updated: August 13th, 2012

Additional State machine diagram for timetable selection

VISIO UML STENCILS

VISIO UML STENCILS

The UML stencil for Microsoft Visio supports complete UML, i.e. UML use case diagram, class diagram, package diagram, object diagram, interaction diagram, sequence diagram, communication diagram, interaction overview diagram, activity diagram, state machine diagram, component diagram, deployment diagram, profile diagram, timing diagram, and all symbols of the UML.

LTspice XVII

LTspice XVII

LTspice XVII is an analog circuit simulation software tool. This program is a partial rewrite of LTspice IV with a modern graphics library for native multi-monitor support. It features: Unicode (use any character of any living language), new device equations (IGBT, soft recovery, and an arbitrary state machine), editors for most SPICE syntax commands, and more.

  • Publisher: Linear Technology Corporation
  • Home page: www.linear.com
  • Last updated: October 7th, 2021
Deeds - Digital Electronics Education and Design Suite

Deeds - Digital Electronics Education and Design Suite

Deeds: Digital Electronics Education and Design Suite is a set of educational tools for Digital Electronics. It covers various areas of digital electronics, like combinational logic networks, sequential logic networks, custom circuit blocks design, micro-computer programming, and more.

HDL Designer

HDL Designer

HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.

VBoxHeadlessTray

VBoxHeadlessTray

VBoxHeadlessTray is simple Windows app that runs a VirtualBox VM as a tray icon. You can customize the context menu that appears when clicking on the VBoxHeadlessTray tray icon, through VBox Guest Properties. If a VBoxHeadlessTray machine is running when Windows is shutdown, it will automatically save the machine's state.

  • Publisher: Topten Software
  • Last updated: February 15th, 2016
UrJTAG

UrJTAG

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications.

FSMDesigner

FSMDesigner

FSMDesigner is an open source C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits. You can also export your FSM to Verilog HDL or VHDL.

  • Publisher: Benjamin Bruno, Frank,Mondrian,Richard Leys
  • Last updated: February 17th, 2014
Visual Paradigm Project Viewer

Visual Paradigm Project Viewer

Visual Paradigm Project Viewer is a program that allows you to view the content of projects created in VP-UML, Logizian, and Agilian. You can open VP-UML projects such as Composite Structure Diagrams, CRC Card Diagrams, Sequence Diagrams, and State Machine Diagrams.

  • Publisher: Visual Paradigm International Ltd.
  • Last updated: March 16th, 2016
JTAG Commander

JTAG Commander

Features: -Total JTAG State Machine control -Any size scan chain, any number of devices, any order -Runs SVF, XSVF, JAM files for programming FPGA/CPLD devices -Uses standard BSDL files or manual information entry -Creates SVF code for system testuses usbDemon interface

  • Publisher: Macraigor Systems
  • Last updated: August 30th, 2014
ATTAC

ATTAC

ATTAC supports any universe size and the windows version runs on Windows 95/98/NT/2000. ATTAC v4 has the same look and feel of the version 3 but has a slightly different interface.ATTAC is now written fully in C which means it is much faster. Bust lists work much better, and the data parsing is much better due to ATTAC's dynamic state machine.

  • Publisher: Trancite Logic Systems
  • Home page: www.tw-attac.com
  • Last updated: November 23rd, 2011
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